1. Field of the Invention
The present invention relates to a high breakdown voltage semiconductor device, and more particularly to a high breakdown voltage and low loss high breakdown voltage semiconductor device used for various power supply devices.
2. Description of the Background Art
High breakdown voltage semiconductor devices used for switching power sources, inverter devices or the like have been improved to power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), SIT (Static Induction Thyristor) and the like and further to IGBT (Insulated Gate Bipolar Transistor) to achieve fast switching characteristic, low on-state voltage and the like in response to demand for high efficiency and miniaturization of the devices. While optimization of structures of these conventional devices has been actively promoted, demands for the devices with still higher frequency and miniaturization of the devices, and more inexpensive devices are difficult to meet and thus some new approach need be taken.
Since conventional high breakdown voltage semiconductor devices are provided with a thick, high relative resistance drift region at a main current path to obtain high breakdown voltage, a device with higher breakdown voltage has larger voltage drop at this portion and its on-state voltage is increased. In particular, a power MOSFET and an SIT of a so-called unipolar device which use only majority carrier for conduction are capable of fast-switching but have high on-state voltage and it has been believed that the trade-off relation between on-state voltage and breakdown voltage cannot exceed a limit characteristic to semiconductor material known as the so-called silicon limit.
For IGBT, a small amount of minority carrier is introduced to a drift region to increase conductivity and thus the trade-off relation between on-state voltage and breakdown voltage has been greatly improved. However, since switching thereof is accompanied with a transient phenomenon caused by minority carrier accumulation effect, thereby increasing switching loss and since a pn junction for introducing minority carrier is provided at a main current path, an on-state voltage equal to or less than the voltage drop cannot be achieved. Thus, for IGBT, it has been difficult to decrease on-state voltage to approximately 1V or less in a device with a breakdown voltage on the order of several hundreds volts.
For bipolar transistors and bipolar mode SITs, minority carrier is supplied from a base or a gate terminal. Thus, while voltage drop due to a pn junction is not caused, switching loss is increased, and also a large base (gate) forward current (approximately 1/10 of a main current for a device with a breakdown voltage on the order of several hundreds volts) need be supplied to increase carrier density to a saturation state, disadvantageously leading to large drive loss.
In order to overcome such limitations on conventional high breakdown voltage devices, a device having a structure in cross section such as that shown in FIG. 58 has been suggested, for example, in U.S. Pat. No. 5,216,275.
The structure shown in FIG. 58 is an example in which the technique disclosed in the above document is applied to a trench gate type power MOSFET and a drift region, which is formed of a high resistivity n type semiconductor in a conventional device, is substituted with a repeat structure of narrow n type region 301 and p type region 302.
The above document does not specifically describe a positional relation between a gate 309 which forms a channel and a p type well 303 which forms a back gate, and pn repeat structure 301 and 302. However, the channel and p type well 303 need be connected to n type region 301 and p type region 302, respectively, as shown in the figure. The above document suggests that it is now important that the amount of the impurity in n type region 301 is equal to that of the impurity in p type region 302 and that the width of each of regions 301 and 302 need be sufficiently narrow.
When a device of this structure is in an on-state, an n channel is induced by MOS gate 309 at a surface of p type well 303 opposite to MOS gate 309 with a gate insulating layer 308 disposed therebetween. Then, electronic current passes the route from a drain n.sup.+ region 304 via n type region 301 and the n type channel to a source n.sup.+ diffusion region 305. If MOS gate 309 is sufficiently biased to suppress voltage drop at the channel portion, the on-state voltage is generally determined depending on the voltage drop caused by the resistance of n type region 301. A on-state resistance Ron per unit area is given by the following relation: EQU Ron.apprxeq.Ld/(q.times.Nd.times..mu.).times.(Wn+Wp)/Wn (1)
wherein
Ld: the length of a drift layer PA1 q: unit charge PA1 Nd: the net impurity concentration in n type region 1 PA1 .mu.: mobility of electrons of n type region 1. PA1 .di-elect cons.: dielectric constant of silicon.
In an off state wherein a drain voltage is as low as approximately 10V, a space-change region is formed along a junction of an n type region portion (formed of drain n.sup.+ region 304 and n type region 301 connected to a drain) and a p type region portion (formed of p type well 303 and p type region 302 connected to a source). Thus, when seen along line 59--59 in the figure, the space-charge region expands from a boundary of the pn junction. As the drain voltage is increased, all of n type region 301 and p type region 302 are depleted, since these regions are thin. When a still higher drain voltage is applied, the space-charge region expands only toward p type well 303 and drain n.sup.+ region 304.
Now FIG. 59 which shows an impurity distribution at the pn repeat structure portion is referred to to discuss electric field strength thereof.
An electric field component at a cross section along line 59--59 in the X direction in FIG. 58 is increased within n type region 301 and decreased within p type region 302 and thus exhibits a continuous triangular waveform, as shown in FIG. 60. When going around a repeat structure portion through p type region 302 and n type region 301, the potential at the cross section along line 59--59 returns to the same level. Thus, an offset point is determined such that an area S.sub.1 (a hatched area) at the positive side of the electric field in the X direction is equal to an area S.sub.2 (a hatched area) at the negative side. When the present model is simplified by Nd=Na (Na: a net impurity concentration of p type region 302), the largest value of the electric field in the X direction is given by the following equation: EQU Ex(max)=q.times.Nd.times.Wn/2/.di-elect cons. (2)
An electric field strength at a cross section along line 60--60 exhibits a distribution in the shape of a rectangle or trapezoid. If the condition that the amount of the impurity in n type region 301 is equal to that of the impurity in p type region 302, a rectangular electric field distribution is obtained. When the amount of the impurity in n type region 301 is relatively larger the strength of an electric field closer to the source (S) is increased, as is typical with a device having a typical n type drift layer.
Here, a breakdown voltage Vbr of a device is almost determined with the largest value of the electric field reaching a critical electric field strength Ec (for silicon, Ec.apprxeq.2e5V/cm(2.times.10.sup.5 V/cm)), and thus when Na=Nd, the following relation can be obtained: EQU Vbr.apprxeq.Ec.times.Ld (3)
According to expression (1), while an impurity concentration Nd of n type region 301 need only be increased to reduce an on-state voltage (on-state resistance), an impurity concentration Na of p type region 302 is also increased to maintain breakdown voltage. As the absolute value of these impurity concentrations is increased, the gradient of an electric field along the X direction in an off state becomes steep. Then, when the largest value Ex(max) of the electric field approaches a critical electric field, breakdown voltage no longer attains a value expected in expression (3). Thus, the following relation is required: EQU Wn&lt;2.times..di-elect cons..times.Ec/(q.times.Nd) (4)
The on-state resistance is: EQU Ron=Vbr.times.(Wn+Wp)/(2.times..di-elect cons..times..mu..times.Ec)(5)
and thus if Wn and Wp are decreased, the on-state resistance can be extremely decreased. While an on-state resistance in this structure is proportional to the breakdown voltage raised to the first power, an on-state resistance in a power MOSFET which employs a conventional, simple high resistance drift region is increased in proportional to the breakdown voltage raised to the second power (which, more specifically, also can be the breakdown voltage raised to the 2.6th power, taking into consideration the dependence of a critical electric field on the impurity concentration of the drift layer). Thus, it is appreciated that if a fine pn repeat structure as shown in FIG. 58 can be built in, a high breakdown voltage and low on-state voltage device can be obtained.
The above document describes that the pn repeat structure shown in FIG. 58 can be obtained by epitaxially growing silicon which selectively contains an impurity at an etched trench or by causing nuclear transformation by selective neutron radiation. However, any of these methods, in fact, hardly has the possibility of achieving a pn repeat structure. This will be described hereinafter in detail with reference to each manufacturing method shown in the figures.
It should be noted that the above document describes the above manufacturing methods in the form of text and thus the following description by means of the figures is derived from the text.
FIGS. 62-64 are schematic cross sectional views for illustrating a method of producing a pn repeat structure by epitaxial growth method in the order of process step. Referring to FIG. 62, an n.sup.- epitaxial layer 301 is formed by epitaxial growth method on an n.sup.+ region 304 which serves as a drain n+region.
Referring to FIG. 63, n.sup.- epitaxial layer 301 is anisotropically etched with n.sup.- epitaxial layer 301 masked by a mask 310 formed of, for example, a silicon oxide film. This causes n.sup.+ region 304 to be exposed and a trench 301a is formed in n.sup.- epitaxial layer 301. Then mask 310 is removed.
Referring to FIG. 64, a p.sup.- epitaxial layer 302 is selectively formed in trench 301a by epitaxial growth method. Thus a pn repeat structure is formed by epitaxial growth method.
With such an epitaxial growth method, a film being formed grows while sucking an impurity closer to a substrate, as is commonly known as autodope phenomenon. Thus, even for a growth at a low temperature of approximate 800.degree. C., an impurity closer to a substrate (an impurity in n.sup.- epitaxial layer 301) will be readily diffused into p.sup.- epitaxial layer 302 during the growth of p.sup.- epitaxial layer 302. Thus, clear p- and n-type impurity layers 301 and 302 in a pn repeat structure cannot be formed in a micron-order fine repeat structure.
Furthermore, it is known that impurity concentration in epitaxial growth method can be controlled by at best approximately 5% and that it is difficult to control by even 10% for the present case in which the value of the impurity concentration of a p type impurity layer is required to be close to that of the impurity concentration of an n type impurity layer.
FIGS. 65 and 66 are schematic cross sectional views for illustrating a method of producintrenchn repeat structure by nuclear transformation caused by neutron radiation in the order of process step. Referring first to FIG. 65, a p.sup.- epitaxial layer 302 is formed on an n.sup.+ region 304 which serves as a drain n.sup.+ region by epitaxial growth method.
Referring to FIG. 66, a mask 350 is used and p.sup.- epitaxial layer 302 is selectively irradiated with neutron ray. Thus, nuclear transformation is caused in part of silicon (Si) to produce phosphorus (P). The phosphorus is an n type dopant and thus an n.sup.- layer 301 is formed in p.sup.- epitaxial layer 302 irradiated with neutron ray. Thus nuclear transformation by neutron radiation forms a pn repeat structure.
For the nuclear transformation by selective neutron radiation, presently there is not a mask material required for forming patterns of micron size. More specifically, while a mask requires a light shielding film for shielding neutron ray radiation, a material typically used for a light shielding film is too thin to shield neutron ray in forming patterns of micron size. Furthermore, since parallel neutron flux cannot be obtained, it is impossible to achieve fine fabrication by the selective neutron ray radiation described above.
As described above, while the structure described in the above document has the possibility of greatly improving the trade-off between the breakdown voltage and on-state voltage of existing devices, there also is a fatal disadvantage that the structure cannot be achieved.